Publications of Jonathan W. Greene

(Engineering-Related)

(See here for chemistry-related publications.)

Journal and Conference Papers

  1. B. Barzen, A. Reais-Parsi, E. Hung, M. Kang, A. Mishchenko, J. W. Greene, J. Wawrzynek
    "Narrowing the Gap: Academic FPGA Synthesis is Catching Up With the Industry"
    2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)
  2. Gabriel Barajas, Jonathan W. Greene, Fei Li, James Tandon
    "Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models"
    2023 24th International Symposium on Quality Electronic Design (ISQED)
  3. Jonathan W. Greene
    "FPGA Mux Usage and Routability Estimates without Explicit Routing"
    FPGA '23 Proceedings of the 2023 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2023
  4. Jonathan W. Greene
    "Exact Mapping of Rewritten Linear Functions to Configurable Logic"
    Proceedings of the Fifth International Workshop on FPGAs for Software Programmers, FSP 2018
  5. Wenyi Feng, Jonathan W. Greene, Alan Mishchenko
    "Improving FPGA Performance with a S44 LUT Structure"
    FPGA '18 Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
  6. Alan Mischchenko, Robert Brayton, Wenyi Feng, Jonathan W. Greene
    ""Technology Mapping into General Programmable Cells"
    FPGA '15 Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
  7. Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu
    "Rent's rule based FPGA packing for routability optimization"
    FPGA '14 Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays, 2014
  8. Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner
    "A 65nm flash-based FPGA fabric optimized for low cost and power"
    FPGA '11 Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, 2011
  9. K. Vorwerk, A. Kennings, J. Greene
    "Improving Simulated Annealing-Based FPGA Placement with Directed Moves"
    IEEE Trans. Computer-Aided Design 28:2, Feb. 2009, pp. 179-192.
  10. W. Feng, J. Greene,
    "Post-Placement Interconnect Entropy"
    IEEE Trans. VLSI Systems 15:8, Aug 2007, pp. 945-948.
  11. K. Vorwerk, A. Kennings, J. Greene, and D. Chen,
    "Improving Annealing via Directed Moves"
    Proc. 17th Int'l Conf. Field Programmable Logic and Applications, Amsterdam, 2007.
  12. Wenyi Feng, Jonathan W. Greene
    "Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?"
    SLIP '06 Proceedings of the 2006 international workshop on System-level interconnect prediction, 2006
  13. Jonathan W. Greene, Esmat Hamdy, Sam Beal
    "Antifuse Field Programmable Gate Arrays"
    Invited article, Proc. IEEE, 18:7, July 1993.
  14. Vwani Roychowdhury, Jonathan W. Greene, Abbas El Gamal
    "Segmented Channel Routing"
    IEEE Trans. on Computer Aided Design, 12:1, Jan. 1993, 79-95.
  15. Abbas El Gamal, Jonathan W. Greene, Vwani Roychowdhury
    "Segmented Channel Routing is Nearly as Efficient as Channel Routing (and Just as Hard)"
    Proc. Univ. Calif. Santa Cruz Conf. on Advanced Research in VLSI, 1991.
  16. Jonathan W. Greene, Vwani Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal
    "Segmented Channel Routing"
    DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference, 1990
  17. M. Ahrens, A. El Gamal, D. Galbraith, J. Greene, S. Kaptanolglu, et al.
    "An FPGA Family Optimized for High Densities and Reduced Routing Delay"
    Proc. IEEE Custom Integrated Circuits Conf., 1990.
  18. A. El Gamal, J. Greene, J. Reyneri, E. Rogoyski, K. El-Ayat, and A. Mohsen
    "An Architecture for Electrically Configurable Gate Arrays"
    IEEE J. Solid-State Circuits, 24:2, 1989, 394-398.
  19. A. El Gamal, J. Greene, J. Reyneri, E. Rogoyski, K. El-Ayat, and A. Mohsen
    "An Architecture for Electrically Configurable Gate Arrays"
    Proc. IEEE Custom Integrated Circuits Conf., 1988.
  20. D. Gluss, A. El Gamal, J. Greene, P. Ang
    "A Multiplier-Accumulator Silicon Compiler"
    Proc. IEEE Custom Integrated Circuits Conf., 1986.
  21. A. El Gamal, D. Gluss, P. Ang, J. Greene, J. Reyneri
    "A CMOS 32-bit Optimized Wallace Tree Multiplier-Accumulator"
    Digest of Technical Papers, IEEE Int'l Solid-State Circuit Conf., 1986.
  22. J. Greene
    "Layout-to-Layout Compaction for Technology Conversion"
    VLSI Systems Design, Nov. 1986.
  23. J. Greene, K. Supowit
    "Simulated Annealing without Rejected Moves"
    IEEE Trans. Computer Aided Design, Jan 1986.
  24. Jonathan W. Greene, Abbas El Gamal
    "Configuration of VLSI Arrays in the Presence of Defects"
    Journal of the ACM (JACM), 1984
  25. A. El Gamal, J. Greene, K. Pang
    "VLSI Complexity of Coding"
    Proc. MIT Conf. on Advanced Research in VLSI, 1984.
  26. J. Greene, A. El Gamal
    "Area and Delay Penalties in Restructurable Wafer-Scale Arrays"
    Proc. Caltech Conf. on VLSI, 1983.
  27. E. Karnin, J. Greene, M. Hellman
    "On Secret Sharing Systems"
    IEEE Trans. Inform. Theory, Jan. 1983.
  28. J. Greene, A. El Gamal,
    "Storage Rates for a Memory with a Selector"
    IEEE Int'l. Symp. on Information Theory, 1982.

Patents

    See here.

Dissertation

Configuration of VLSI Arrays in the Presence of Defects
Stanford Univ. Dept. Electrical Engineering, 1984.
(Established the possibility of area-efficient defect-tolerant circuits of unbounded size.)